M95512-R datasheet(20/48 Pages) STMICROELECTRONICS

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Instructions

M95512-W, M95512-R

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Doc ID 11124 Rev 13

6.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

must have been executed.

The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low,

sending the instruction code and the data byte on Serial Data input (D) and driving Chip

Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)

that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock

(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.

Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write

cycle whose duration is tW (specified in Table 16 and Table 18). The instruction sequence is

shown in Figure 11.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed

Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is

also reset when the Write cycle tW is complete.

The Write Status Register (WRSR) instruction allows the user to change the values of the

BP1, BP0 and SRWD bits:

●

The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only,

as defined in Table 6.

●

The SRWD bit (Status Register Write Disable bit), depending on the signal applied on

the Write Protect pin (W), allows the user to set or reset the write protection mode of

the Status Register. When the Status Register is in the Write-protected mode, the Write

Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR

instruction (after tW).

The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5,

b4, b1, b0. They are always read as 0.

Figure 11.

Write Status Register (WRSR) sequence

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

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