M95256 datasheet(27/48 Pages) STMICROELECTRONICS

27 / 48 page

M95256-DR, M95256, M95256-W, M95256-R

Delivery state

Doc ID 12276 Rev 11

27/48

Delivery state

The device is delivered with the memory array set at all 1s (FFh). The Status Register Write

Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such

as the Read from Memory Array and Read Status Register instructions) have been clocked

into the device.

Figure 17 shows an example of three memory devices connected to an MCU, on an SPI

bus. Only one memory device is selected at a time, so only one memory device drives the

Serial Data output (Q) line at a time, the other memory devices are high impedance.

Figure 17.

Bus master and memory devices on the SPI bus

The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

The pull-up resistor R (represented in Figure 17) ensures that a device is not selected if the

bus master leaves the S line in the high-impedance state.

In applications where the bus master might enter a state where all SPI bus inputs/outputs

would be in high impedance at the same time (for example, if the bus master is reset during

AI12304b

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3

CS2

CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

VCC

VSS

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