±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

_______________________________________________________________________________________

5

VL

0.5V

POK

COMPARATOR

GM

LDO

CONTROLLER 1

LDO

CONTROLLER 2

LDO

CONTROLLER 3

0.5V

REF

VL

UVLO

EN1

POK1

GND

EN2

POK2

EN3

POK3

FB3

DRV3

DRV2

FB1

FB2

DRV1

MAX8563

MAX8564

MAX8564A

Functional Diagram

Pin Description

NAME

PIN

MAX8563

MAX8564/

MAX8564A

FUNCTION

1

DRV1

DRV1

Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 1.

DRV1 is internally pulled to ground when EN1 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

2FB1

FB1

Feedback Input for Output 1. Connect to the center of a resistor-divider between output 1 and GND to

set the output voltage of output 1. The feedback regulation voltage is 0.500V. See the Output Voltage

Setting section.

3

EN1

EN1

Enable Control for Output 1. Drive logic high to enable output 1, or logic low to disable the

4

POK1

POK1

Output 1 Power-Good Signal. Open-drain output pulls low when output 1 is 12% below the

nominal regulated voltage.

5

GND

GND

Ground

—

POK2

Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the

nominal regulated voltage.

6

N.C.

—

No Internal Connection