M95256-D-CS3GSLASHA datasheet(13/48 Pages) STMICROELECTRONICS

13 / 48 page

M95256-DR, M95256, M95256-W, M95256-R

Operating features

Doc ID 12276 Rev 11

13/48

4.2

Status Register

Figure 4 shows the position of the Status Register in the control logic of the device. The

Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. For a detailed description of the Status Register bits,

see Section 5.3: Read Status Register (RDSR).

4.3

Data protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

●

Write and Write Status Register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

●

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

–

Write Disable (WRDI) instruction completion

–

Write Status Register (WRSR) instruction completion

–

Write (WRITE) instruction completion

●

The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

●

The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

●

The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

●

The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2.

Write-protected block size

Status Register bits

Protected block

Protected array addresse

BP1

BP0

M95256, M95256-W, M95256-R

none

Upper quarter

6000h - 7FFFh

Upper half

4000h - 7FFFh

Whole memory

0000h - 7FFFh

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