数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

M95256-D-CS3G/A 数据表(PDF) 35 Page - STMicroelectronics

部件名 M95256-D-CS3G/A
功能描述  256 Kbit serial SPI bus EEPROM with high-speed clock
PDF  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95256-D-CS3G/A 数据表(HTML) 35 Page - STMicroelectronics

Back Button M95256-D-CS3G/A Datasheet HTML 31Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 32Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 33Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 34Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 35Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 36Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 37Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 38Page - STMicroelectronics M95256-D-CS3G/A Datasheet HTML 39Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 35 / 48 page
background image
M95256-DR, M95256, M95256-W, M95256-R
DC and AC parameters
Doc ID 12276 Rev 11
35/48
Table 18.
AC characteristics, new M95256-W, device grade 6
Test conditions: VCC = 2.5 to 5.5 V,
TA = -40 to 85 °C
CL = 100 pF
New products (process K,
preliminary information)
CL = 30 pF
Unit
Symbol
Alt.
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
fC
fSCK
Clock frequency
D.C.
5
D.C.
10
D.C.
20
MHz
tSLCH
tCSS1
S active setup time
90
30
15
ns
tSHCH
tCSS2
S not active setup time
90
30
15
ns
tSHSL
tCS
S deselect time
100
40
20
ns
tCHSH
tCSH
S active hold time
90
30
15
ns
tCHSL
S not active hold time
90
30
15
ns
tCH
(1)
tCLH
Clock high time
90
45
20
ns
tCL
(1)
tCLL
Clock low time
90
45
20
ns
tCLCH
(2)
tRC
Clock rise time
122
µs
tCHCL
(2)
tFC
Clock fall time
122
µs
tDVCH
tDSU
Data in setup time
20
10
5
ns
tCHDX
tDH
Data in hold time
30
10
10
ns
tHHCH
Clock low hold time after HOLD not
active
70
30
15
ns
tHLCH
Clock low hold time after HOLD active
40
30
15
ns
tCLHL
Clock low setup time before HOLD active
00
0
ns
tCLHH
Clock low setup time before HOLD not
active
00
0
ns
tSHQZ
(2)
tDIS
Output disable time
100
40
20
ns
tCLQV
tV
Clock low to output valid
60
40
20
ns
tCLQX
tHO
Output hold time
00
0
ns
tQLQH
(2)
tRO
Output rise time
50
40
20
ns
tQHQL
(2)
tFO
Output fall time
50
40
20
ns
tHHQV
tLZ
HOLD high to output valid
50
40
20
ns
tHLQZ
(2)
tHZ
HOLD low to output High-Z
100
40
20
ns
tW
tWC
Write time
555
ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2.
Value guaranteed by characterization, not tested in production.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com