PPC8567ECVTANJGA datasheet(3/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

MPC8568E Overview

1.1

MPCP8568E Key Features

•

High-performance, Power Architecture® e500v2 core with 36-bit physical addressing

•

512 Kbytes of level-2 cache

•

QUICC Engine (QE)

•

Integrated security engine with XOR acceleration

•

Two integrated 10/100/1Gb enhanced three-speed Ethernet controllers (eTSECs) with TCP/IP

acceleration and classification capabilities

•

DDR/DDR2 memory controller

•

Table lookup unit (TLU) to access application-defined routing topology and control tables

•

32-bit PCI controller

•

A 1x/4x Serial RapidIO® and/or x1/x2/x4 PCI Express interface. If x8 PCI Express is needed, then

RapidIO is not available due to the limitation of the pin multiplexing.

•

Programmable interrupt controller (PIC)

•

Four-channel DMA controller, two I2C controllers, DUART, and local bus controller (LBC)

NOTE

The MPC8568E and MPC8567E are also available without a security

engine in a configuration known as the MPC8568 and MPC8567. All

specifications other than those relating to security apply to the MPC8568

and MPC8567 exactly as described in this document.

1.2

MPC8568E Architecture Overview

1.2.1

e500 Core and Memory Unit

The MPC8568E contains a high-performance, 32-bit, Book E–enhanced e500v2 Power Architecture core.

In addition to 36-bit physical addressing, this version of the e500 core includes the following:

•

Double-precision floating-point APU—Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs

•

Embedded vector and scalar single-precision floating-point APUs—Provide an instruction set for

single-precision (32-bit) floating-point instructions

The MPC8568E also contains 512 Kbytes of L2 cache/SRAM, as follows:

•

Eight-way set-associative cache organization with 32-byte cache lines

•

Flexible configuration (can be configured as part cache, part SRAM)

•

External masters can force data to be allocated into the cache through programmed memory ranges

or special transaction types (stashing).

•

SRAM features include the following:

— I/O devices access SRAM regions by marking transactions as snoopable (global).

— Regions can reside at any aligned location in the memory map.

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