PPC8567ECVTANJGA datasheet(7/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

MPC8568E Overview

up to four banks of memory. The MPC8568E supports bank sizes from 64 Mbytes to 4 Gbytes. Nine

column address strobes (MDM[0:8]) are used to provide byte selection for memory bank writes.

The MPC8568E can be configured to retain the currently active SDRAM page for pipelined burst accesses.

Page mode support of up to 16 simultaneously open pages (32 for DDR2) can dramatically reduce access

latencies for page hits. Depending on the memory system design and timing parameters, using page mode

can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page.

Using ECC, the MPC8568E detects and corrects all single-bit errors and detects all double-bit errors and

all errors within a nibble.

The MPC8568E can invoke a level of system power management by asserting the MCKE SDRAM signal

on-the-fly to put the memory into a low-power sleep mode.

1.2.7

Table Lookup Unit (TLU)

The table lookup unit (TLU) provides access to application-defined routing topology and control tables in

external memory. It accesses an external memory array attached to the local bus controller (LBC).

Communication between the CPU and the TLU occurs via messages passed through the TLU’s

memory-mapped configuration and status registers.

The TLU provides resources for efficient generation of table entry addresses in memory, hash generation

of addresses, and binary table searching algorithms for both exact-match and longest-prefix-match

strategies.It supports the following TLU complex table types:

•

Hash-Trie-Key table for hash-based exact-match algorithms

•

Chained-Hash table for partially indexed and hashed exact-match algorithms

•

Longest-prefix-match algorithm

•

Flat-Data table for retrieving search results and simple indexed algorithms

1.2.8

PCI Controller

The MPC8568E supports one 32-bit PCI controller, which supports speeds of up to 66 MHz. Other features

include:

•

Compatible with the PCI Local Bus Specification, Revision 2.2, supporting 32- and 64-bit

addressing

•

Can function as host or agent bridge interface

•

As a master, supports read and write operations to PCI memory space, PCI I/O space, and PCI

configuration space

•

Can generate PCI special-cycle and interrupt-acknowledge commands. As a target, it supports read

and write operations to system memory as well as configuration accesses.

•

Supports PCI-to-memory and memory-to-PCI streaming, memory prefetching of PCI read

accesses, and posting of processor-to-PCI and PCI-to-memory writes

•

PCI 3.3-V compatible with selectable hardware-enforced coherency

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