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PPC8567ECVTANJGA 数据表(PDF) 135 Page - Freescale Semiconductor, Inc |
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PPC8567ECVTANJGA 数据表(HTML) 135 Page - Freescale Semiconductor, Inc |
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135 / 139 page  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 135 System Design Information Figure 75. JTAG Interface Connection 25.9 Guidelines for High-Speed Interface Termination 25.9.1 Unused output Any of the outputs that are unused should be left unconnected. These signals are: •SD_TX[7:0] HRESET HRESET From Target Board Sources HRESET 13 SRESET SRESET NC NC 11 VDD_SENSE 6 5 1 15 10 Ω 10 k Ω 10 k Ω 10 k Ω OVDD OVDD OVDD OVDD CHKSTP_IN CHKSTP_IN 8 TMS TDO TDI TCK TMS TDO TDI TCK 9 1 3 4 TRST 7 16 2 10 12 (if any) 14 2 Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented. Connect pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. OVDD OVDD 10 k Ω OVDD TRST 10 k Ω OVDD 10 k Ω 10 k Ω CHKSTP_OUT CHKSTP_OUT 3 13 9 5 1 6 10 15 11 7 16 12 8 4 KEY No pin COP Connector Physical Pin Out 1 2 NC SRESET0 SRESET1 3. Use a NOR gate with sufficient drive strength to drive two inputs. 3 |
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