SC28L201 datasheet(2/110 Pages) NXP

2 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

2 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Features

s Member of IMPACT family: 3.3 V or 5.0 V,

−40 °C to +85 °C and 80xxx or 68000 bus

interface (I/M modes)

s Bit-by-bit real time transmission error check for high data integrity systems

s Full-duplex independent asynchronous receiver/transmitter

s 256 character FIFOs for receiver and transmitter

s Powers up to 9600 baud, 8 bits, no parity, 1 stop bit, interrupt disabled, all I/O set to

input

s Pin programming to 68000 or 80xxx bus interface

s Three character recognition system, used as:

x General purpose character recognition

x Xon/Xoff character recognition

x Address recognition Wake-up (multi-drop or 9-bit) mode

x System provides 4 levels of automation on a recognition event

s Programmable data format

x 5 to 8 data bits plus parity and 9-bit mode

x Odd, even, no parity, or force parity

x 9

⁄

16, 1, 1.5 or 2 stop bits

s 16-bit programmable Counter/Timer

s Programmable baud rate for receiver and transmitter selectable from:

x 27 ﬁxed rates: 50 Bd to 2.0 MBd (includes MIDI rate)

x Other baud rates via external clocks and C/T

x Programmable user-deﬁned rates derived from a programmable Counter/Timer

x External 1

× or 16× clock

s Parity, framing, and overrun error detection

s Line break detection and generation; false start bit detection

s Programmable channel mode

x Normal (full-duplex)

x Automatic echo

x Local loopback

x Remote loopback

x Multi-drop mode (also called ‘Wake-up’ or ‘9-bit’)

s Multifunction 13-bit I/O input port

x Can serve as clock or control inputs

x Change-of-state detection on eight inputs

x Inputs have typically > 100 M

Ω pull-up resistors

x Modem and DMA interface

s Versatile arbitrating interrupt system

x Interrupt system totally supports single query polling

x Output port can be conﬁgured to provide a total of up to six separate interrupt type

outputs that may be wire-ORed (switched to open-drain)

x Each FIFO can be independently programmed for any of 256 interrupt levels

x Watchdog timer for receiver

s Maximum data transfer rates: 1

× clock = 3 Mbit/s; 16× clock = 3.125 Mbit/s

SC28L201 数据表(PDF) 2 Page - NXP Semiconductors

SC28L201 数据表(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载