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MPC5602DPB 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

部件名 MPC5602DPB
功能描述  MPC5602D Microcontroller Product Brief
PDF  27 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC5602DPB 数据表(HTML) 21 Page - Freescale Semiconductor, Inc

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Device family overview
MPC5602D Microcontroller Product Brief, Rev. 3.1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
Source and destination address registers are independently configured to post-increment or remain
constant
Each transfer is initiated by peripheral, CPU, periodic timer interrupt or eDMA channel request
Peripheral DMA request sources include DSPIs, 12-bit ADC, eMIOS and GPIOs
Each eDMA channel able to optionally send interrupt request to CPU on completion of single value
or block transfer
DMA transfers possible between system memories and all accessible memory mapped locations
including peripheral and registers
Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA
channel with total of up to 16 potential request sources
3.5.17
Cross Trigger Unit (CTU)
The CTU enables the synchronization of ADC conversions with a timer event. Its key features are:
Single cycle delayed trigger output trigged by up to 29 input flags/events connected to different
timers in the system
Triggers ADC conversions from any eMIOS channel
Triggers ADC conversions from one dedicated PIT
Maskable interrupt generation whenever a trigger output is generated
1 event configuration register dedicated to each timer event allows to define the corresponding
ADC channel
Acknowledgment signal to eMIOS/PIT for clearing the flag
Synchronization with ADC to avoid collision
3.5.18
Serial Communication Interface Module (LINFlex)
The LINFlex on the MPC5602D features the following:
3 LINFlex modules supported
Supports LIN master mode, LIN slave mode and UART mode
1 module supporting LIN master and slave mode; 2 modules supporting LIN master mode
LIN state machine compliant to LIN 1.3, 2.0 and 2.1 specifications
Handles LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— Message buffer to store identified and up to 8 data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors
– Sync field
– Delimiter
–ID parity



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