Device family overview

MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

13

3.5.2

Crossbar Switch (XBAR)

The following summarizes the MPC5602D’s implementation of the crossbar switch:

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3 master ports:

— CPU instruction bus

— CPU load/store bus

—eDMA

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Multiple bus slaves to enable access to flash memory, SRAM and peripherals

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Crossbar supports up to 2 consecutive transfers at any one time

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32-bit internal address bus, 32-bit internal data bus

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Fixed priority arbitration based on port master

3.5.3

Interrupt Controller (INTC)

The MPC5602D implements an interrupt controller that features the following:

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Unique 9-bit vector for each of the 155 separate interrupt sources

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8 software triggerable interrupt sources

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16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

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Ability to modify the ISR or task priority

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External high priority interrupt directly accessing the main core critical interrupt mechanism

3.5.4

System Integration Unit Lite (SIUL)

The SIUL features the following:

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Up to 4 levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of

device functions for each package

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Centralized general purpose input output (GPIO) control of up to 79 input/output pins (package

dependent)

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All GPIO pins independently configurable to support pull-up, pull down, or no pull

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Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

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All peripheral pins can be alternatively configured as both general purpose input or output pins

except ADC channels which support alternative configuration as general purpose inputs, with

selected pins able to also support outputs

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Direct readback of the pin value supported on all digital output pins through the SIUL

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Configurable digital input filter that can be applied to up to 16 general purpose input pins for noise

elimination on external interrupts

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Register configuration protected against change with soft lock for temporary guard or hard lock to

prevent modification until next reset

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Support for two 32-bit virtual ports via the DSPI serialization