70592C datasheet(130/314 Pages) MICROCHIP

130 / 314 page

PIC24HJXXXGPX06A/X08A/X10A

DS70592C-page 130

OSCCON: OSCILLATOR CONTROL REGISTER(1,3)

U-0

R-0

U-0

R/W-y

—

COSC<2:0>

—

NOSC<2:0>(2)

bit 15

bit 8

R/W-0

U-0

R-0

U-0

R/C-0

U-0

R/W-0

CLKLOCK

—LOCK

—CF

—

LPOSCEN

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

C = Clear only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

111 = Fast RC oscillator (FRC) with Divide-by-n

110 = Fast RC oscillator (FRC) with Divide-by-16

101 = Low-Power RC oscillator (LPRC)

100 = Secondary oscillator (SOSC)

011 = Primary oscillator (XT, HS, EC) with PLL

010 = Primary oscillator (XT, HS, EC)

001 = Fast RC oscillator (FRC) with PLL

000 = Fast RC oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits(2)

111 = Fast RC oscillator (FRC) with Divide-by-n

110 = Fast RC oscillator (FRC) with Divide-by-16

101 = Low-Power RC oscillator (LPRC)

100 = Secondary oscillator (SOSC)

011 = Primary oscillator (XT, HS, EC) with PLL

010 = Primary oscillator (XT, HS, EC)

001 = Fast RC oscillator (FRC) with PLL

000 = Fast RC oscillator (FRC)

bit 7

CLKLOCK: Clock Lock Enable bit

1 = If (FCKSM0 = 1), the clock and PLL configurations are locked

If (FCKSM0 = 0), the clock and PLL configurations may be modified

0 = Clock and PLL selections are not locked, configurations may be modified

bit 6

Unimplemented: Read as ‘0’

bit 5

LOCK: PLL Lock Status bit (read-only)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

Unimplemented: Read as ‘0’

bit 3

CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2

Unimplemented: Read as ‘0’

Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70227) in the

“dsPIC33F/PIC24H Family Reference Manual” for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC

mode as a transition clock source between the two PLL modes.

3: This register is reset only on a Power-on Reset (POR).

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