70592C datasheet(145/314 Pages) MICROCHIP

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DS70592C-page 145

PIC24HJXXXGPX06A/X08A/X10A

11.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKIN) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

11.1

Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 11-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

When a peripheral is enabled and actively driving an

associated pin, the use of the pin as a general purpose

output pin is disabled. The I/O pin may be read, but the

output driver for the parallel port bit will be disabled. If

a peripheral is enabled, but the peripheral is not

actively driving a pin, that pin may be driven by a port.

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

or an output. If the data direction bit is a ‘1’, the pin is

then an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch. Reads from the port

(PORTx), read the port pins, while writes to the port

pins, write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pins will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nonetheless

regarded as a dedicated port because there is no other

competing source of outputs. An example is the INT4

pin.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note 1: This data sheet summarizes the features

of the PIC24HJXXXGPX06A/X08A/X10A

family of devices. However, it is not

intended

comprehensive

reference source. To complement the

information in this data sheet, refer to

Section 10. “I/O Ports” (DS70230) of

the

“dsPIC33F/PIC24H

Family

Reference Manual”, which is available

from

the

Microchip

website

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

The voltage on a digital input pin can be

between -0.3V to 5.6V.

WR LAT +

TRIS Latch

I/O Pin

WR PORT

Data Bus

Data Latch

Read Port

Read TRIS

WR TRIS

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

Read LAT

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