MIC3003 datasheet(32/75 Pages) MICREL

32 / 75 page

Micrel, Inc.

MIC3003

November 2009

M9999-111209-C

hbwhelp@micrel.com or (408) 955-1690

The internal state machine calculates a new table index

each time a new average temperature value becomes

available. This table index is derived from the average

temperature value. The table index is then converted into

a table address for each of the four look-up tables. These

operations can be expressed as:

(10)

where TAVG(n) is the current average temperature; and

TABLE_ADDRESS=INDEX+BASE_ADDRESS

where BASE_ADDRESS is the physical base address of

each table, i.e., 00h, 20h, 40h, 80h, or 60h (tables reside in

the Base address + 4h and Base address + 6h pages of

memory).

At any given time, the current table index can be read in

the LUTINDX register.

Alarms and Warning Flags

There are 20 different conditions that will cause the

MIC3003 to set one of the bits in the WARNx or ALARMx

registers. These conditions are listed in Table 21. The

less critical of these events generate warning flags by

setting a bit in WARN0 or WARN1. The more critical

events cause bits to be set in ALARM0 or ALARM1.

An event occurs when any alarm or warning condition

becomes true. Each event causes its corresponding

status bit in ALARM0, ALARM1, WARN0, or WARN1 to

be set. This action cannot be masked by the host. IF

OEMCFG-4 bits [7-4] are set to 0 (default value), the

status bit will remain set until the host reads that

particular status register, a power on-off cycle occurs, or

the host toggles TXDISABLE.

If TXDISABLE is asserted at any time during normal

operation, A/D conversions continue. The A/D results for

all parameters will continue to be reported. All events will

be reported in the normal way. If they have not already

been individually cleared by read operations, when

TXDISABLE is deasserted, all status registers will be

cleared.

Control and Status I/O

The logic for the transceiver control and status I/O is shown

schematically in Figure 13. Note that the internal drivers on

RXLOS/TRSOUT, RRSOUT/GPO, QGPO, and TXFAULT

are all open-drain. These signals may be driven either by

the internal logic or external drivers connected to the

corresponding MIC3003 pins. In any case, the signal level

appearing at the pins of the MIC3003 will be reported in the

control register status bits.

Note that the control bits for TX_DISABLE and RRSOUT,

TRSOUT, and the status bits for TXFAULT and RXLOS do

not meet the timing requirements as specified in the SFP

MSA or the GBIC Specification, revision 5.5 (SFF-8053) for

the hardware signals. The speed of the SMBus serial

interface limits the rate at which these functions can be

manipulated and/or reported. The response time for the

control and status bits is given in the “Electrical

Characteristics” subsection.

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