PC33882R2 datasheet(9/31 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V

≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125°C, unless otherwise

noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING

Output Rise Time (29)

1.0

–

μs

Output Fall Time (29)

1.0

–

μs

Output Turn-ON Delay Time (30)

tDLY(ON)

1.0

–

μs

Output Turn-OFF Delay Time (31)

tDLY(OFF)

1.0

–

μs

Output Short Fault Sense Time (32)

RLOAD = < 1.0 V

tSS

–

100

μs

Output Short Fault Refresh Time (33)

RLOAD = < 1.0 V

tREF

3.0

4.5

6.0

Output OFF Open Load Sense Time (34)

tOS(OFF)

100

μs

Output ON Open Load Sense Time (35)

tOS(ON)

3.0

–

Output Short Fault ON Duty Cycle (36)

SCDC

0.42

–

3.22

DIGITAL INTERFACE TIMING

SCLK Clock High Time (SCLK = 3.2 MHz) (37)

tSCLKH

–

141

SCLK Clock Low Time (SCLK = 3.2 MHz) (37)

tSCLKL

–

141

Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK

Required Setup Time (37)

tLEAD

–

140

Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS

Required Setup Time (37)

tLAG

–

SI, CS, SCLK Incoming Signal Rise Time (37)

tRSI

–

SI, CS, SCLK Incoming Signal Fall Time (37)

tFSI

–

Notes

29.

Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15

Ω resistive load to a VBAT

of 15 V, VPWR = 15 V.

30.

Output Turn-ON Delay Time measured from rising edge (3.0 V) VIN (CS for serial) to 90% VO using a 15 Ω load to a VBAT of 15 V,

VPWR = 15 V.

31.

Output Turn-OFF Delay Time measured from falling edge (1.0 V) VIN (3.0 V rising edge of CS for serial) to 10% VO using a 15 Ω load

to a VBAT of 15 V, VPWR = 15 V.

32.

The shorted output is turned ON during tSS to retry and check if the short has cleared. The shorted output is in current limit during tSS.

The tSS is measured from the start of current limit to the end of current limit.

33.

The Short Fault Refresh Time is the waiting period between tSS retry signals. The shorted output is disabled during this refresh time.

The tREF is measured from the end of current limit to the start of current limit.

34.

The tOS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault

μs after the faulted output is off.

35.

The tOS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault

register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.

36.

Percent Output Short Fault ON Duty Cycle is defined as (tSS) ÷ (tREF) x 100. This specification item is provided FYI and is not tested.

37.

Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.

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