MPC5646C datasheet(83/114 Pages) FREESCALE

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MPC5646C Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Figure 21. MII receive signal timing diagram

4.18.2

MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency in 2:1 mode and two times

the TX_CLK frequency in 1:1 mode.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of

TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.

Refer to the Fast Ethernet Controller (FEC) chapter of the JPC5604B Reference Manual for details of this option and how to

enable it.

Table 45. MII transmit signal timing1

1 Output pads configured with SRE = 0b11.

Spec

Characteristic

Min

Max

Unit

TX_CLK to TXD[3:0],

TX_EN, TX_ER

invalid

5—

TX_CLK to TXD[3:0],

TX_EN, TX_ER valid

—25

TX_CLK pulse width

high

35%

65%

TX_CLK period

TX_CLK pulse width

low

35%

65%

TX_CLK period

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

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