CY2DP1502

Document Number: 001-56308 Rev. *G

Page 3 of 13

Pinouts

Figure 1. Pin Diagram – 8-Pin SOIC and 8-Pin TSSOP Package

1

2

3

45

6

7

8

Q0

Q0#

Q1

Q1#

IN

IN#

Table 1. Pin Definitions

Pin Number

Pin Name

Pin Type

Description

1,3

Q(0:1)

Output

LVPECL output clocks

2,4

Q(0:1)#

Output

LVPECL complementary output clocks

Power

Ground

6

IN#

Input

LVPECL complementary input clock

7

IN

Input

LVPECL input clock

Power

Power supply

Absolute Maximum Ratings

Parameter

Description

Condition

Min

Max

Unit

Supply voltage

Nonfunctional

–0.5

4.6

V

[2]

Nonfunctional

–0.5

lesser of 4.0

V

[2]

Nonfunctional

–0.5

lesser of 4.0

V

Storage temperature

Nonfunctional

–55

150

°C

Electrostatic discharge (ESD) protection

(Human body model)

JEDEC STD 22-A114-B

2000

–

V

Latch up

Meets or exceeds JEDEC Spec

JESD78B IC Latchup Test

UL–94

Flammability rating

At 1/8 in

V-0

MSL

Moisture sensitivity level

3

Operating Conditions

Parameter

Description

Condition

Min

Max

Unit

Supply voltage

2.5-V supply

2.375

2.625

V

3.3-V supply

3.135

3.465

V

Ambient operating temperature

Commercial

0

70

°C

Industrial

–40

85

°C

Power ramp time

minimum specified voltage (power

ramp must be monotonic).

0.05

500

ms

Note

2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.