PCF8564A_10 datasheet(20/45 Pages) NXP

20 / 45 page

PCF8564A

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Product data sheet

Rev. 02 — 30 September 2010

20 of 45

NXP Semiconductors

PCF8564A

Real time clock and calendar

[1]

Registers marked ‘x’ are undefined at power-on and unchanged by subsequent resets.

8.11.1 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a circuit has been implemented to

disable the POR and speed up functional test of the module. The setting of this mode

requires that the I2C signals on the pins SDA and SCL are toggled as illustrated in

Figure 11. All timings shown are required minimums.

Once the override mode has been entered, the chip immediately stops, being reset, and

normal operation may begin, i.e., entry into the EXT_CLK test mode via I2C access. The

override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1

before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal

operation has no effect, except to prevent entry into the POR override mode.

Table 27.

Address

Bit

00h

Control_1

00001000

01h

Control_2

00000000

02h

Seconds

xxxxxxx

03h

Minutes

xxxxxxxx

04h

Hours

xxxxxxxx

05h

Days

xxxxxxxx

06h

Weekdays

xxxxxxxx

07h

Months

xxxxxxxx

08h

Years

xxxxxxxx

09h

Minute_alarm

xxxxxxx

0Ah

Hour_alarm

xxxxxxx

0Bh

Day_alarm

xxxxxxx

0Ch

Weekday_alarm

xxxxxxx

0Dh

CLKOUT_ctrl

xxxxx0

0Eh

Timer_ctrl

xxxxx1

0Fh

Timer

xxxxxxxx

Allow 500 ns between the edges of either signal.

Fig 11. POR override sequence

mgm664

SCL

500 ns

2000 ns

SDA

8 ms

override active

power-on

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