PCF8564A_10 datasheet(24/45 Pages) NXP

24 / 45 page

PCF8564A

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Product data sheet

Rev. 02 — 30 September 2010

24 of 45

NXP Semiconductors

PCF8564A

Real time clock and calendar

10.3 Interface watchdog timer

During read/write operations, the time counting circuits are frozen. To prevent a situation

where the accessing device becomes locked and does not clear the interface, the

PCF8564A has a built in watchdog timer. Should the interface be active for more than 1 s

from the time a valid slave address is transmitted, then the PCF8564A will automatically

clear the interface and allow the time counting circuits to continue counting.

The watchdog is implemented to prevent the excessive loss of time due to interface

access failure e.g. if main power is removed from a battery backed-up system during an

interface access.

Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The

watchdog will trigger between 1 s and 2 s after receiving a valid slave address.

Fig 18. Master reads word after setting word address (write word address; READ data)

SLAVE ADDRESS

WORD ADDRESS

SLAVE ADDRESS

acknowledgement

from slave

R/W

013aaa034

R/W

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

auto increment

memory word address

auto increment

memory word address

at this moment master transmitter

becomes master receiver and

PCF8564A slave receiver

becomes slave transmitter

last byte

DATA

n bytes

Fig 19. Master reads slave immediately after first byte (READ mode)

SLAVE ADDRESS

DATA

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

R/W

auto increment

word address

mgl665

auto increment

word address

n bytes

last byte

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