PCF8564A datasheet(29/45 Pages) NXP

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PCF8564A

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Product data sheet

Rev. 02 — 30 September 2010

29 of 45

NXP Semiconductors

PCF8564A

Real time clock and calendar

14. Dynamic characteristics

[1]

Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series:

[2]

Unspecified for fCLKOUT = 32.768 kHz.

[3]

All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[4]

A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.

Table 30.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs =40 kΩ; CL = 8 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Oscillator

CL(itg)

integrated load capacitance

[1] 6

Δf

osc/fosc

relative oscillator frequency variation

ΔV

DD = 200 mV;

Tamb =25 °C

0.2

ppm

Quartz crystal parameters

series resistance

100

load capacitance

CLKOUT output

CLKOUT

duty cycle on pin CLKOUT

[2] -50

I2C-bus timing characteristics (see Figure 25)[3][4]

fSCL

SCL clock frequency

400

kHz

tHD;STA

hold time (repeated) START condition

0.6

μs

tSU;STA

set-up time for a repeated START

condition

0.6

μs

tLOW

LOW period of the SCL clock

1.3

μs

tHIGH

HIGH period of the SCL clock

0.6

μs

rise time of both SDA and SCL signals

0.3

μs

fall time of both SDA and SCL signals

0.3

μs

capacitive load for each bus line

400

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

tSU;STO

set-up time for STOP condition

0.6

μs

tw(spike)

spike pulse width

Litg

()

OSCI

OSCO

⋅

()

OSCI

OSCO

()

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