PCF85162 datasheet(6/46 Pages) NXP

6 / 46 page

PCF85162

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Product data sheet

Rev. 3 — 16 June 2011

6 of 46

NXP Semiconductors

PCF85162

Universal LCD driver for low multiplex rates

The host microcontroller maintains the 2-line I2C-bus communication channel with the

PCF85162. The internal oscillator is enabled by connecting pin OSC to pin VSS. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are to the power supplies

(VDD, VSS, and VLCD) and the LCD panel chosen for the application.

7.1 Power-On Reset (POR)

At power-on the PCF85162 resets to the following starting conditions:

• All backplane and segment outputs are set to VLCD

• The selected drive mode is: 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I2C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• Display is disabled

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between VLCD and VSS. The center impedance is

bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode

configuration is selected. The LCD voltage can be temperature compensated externally,

using the supply to pin VLCD.

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

VLCD and the resulting discrimination ratios (D) are given in Table 5.

The resistance of the power lines must be kept to a minimum.

Fig 4.

Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

2Cb

SDA

SCL

OSC

32 segment drives

4 backplanes

LCD PANEL

(up to 128

elements)

PCF85162

SA0

VDD

VSS

VDD

VLCD

013aaa066

≤

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