PCF85162 datasheet(16/46 Pages) NXP

16 / 46 page

PCF85162

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Product data sheet

Rev. 3 — 16 June 2011

16 of 46

NXP Semiconductors

PCF85162

Universal LCD driver for low multiplex rates

• In the static drive mode the same signal is carried by all four backplane outputs and

they can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 32

 4-bit RAM which stores LCD data. There is a one-to-one

correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the

segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,

second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,

BP2, and BP3 respectively.

When display data is transmitted to the PCF85162, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment

numeric display showing all drive modes is given in Figure 12; the RAM filling organization

depicted applies equally to other LCD types.

The display RAM bit map shows the direct relationship between the display RAM addresses and

the segment outputs and between the bits in a RAM word and the backplane outputs.

Fig 11. Display RAM bit map

display RAM addresses/segment outputs (S)

columns

display RAM rows/

backplane outputs

(BP)

rows

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