L6727

Application details

Doc ID 12933 Rev 4

17/34

To place the poles and zeroes of the compensation network, the following suggestions may

be followed:

a)

to 5 k

Ω):

b)

c)

d)

e)

Check that compensation network gain is lower than open loop EA gain;

f)

Estimate phase margin obtained (it should be greater than 45 °) and repeat,

modifying parameters, if necessary.

9.3

Layout guidelines

L6727 provides control functions and high current integrated drivers to implement high-

current step-down DC-DC converters. In this kind of application, a good layout is very

important.

The first priority when placing components for these applications has to be reserved to the

power section, minimizing the length of each connection and loop as much as possible. To

minimize noise and voltage spikes (EMI and losses) power connections (highlighted in

Figure 8) must be part of a power plane and anyway realized by wide and thick copper

traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,

must be close one to the other. The use of multi-layer printed circuit board is recommended.

placed close to the power section in order to eliminate the stray inductance generated by the

copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be

connected near the HS drain.

Use proper VIAs number when power traces have to move between different planes on the

PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the

R

F

R

FB

----------

F

0dB

F

LC

------------

ΔV

OSC

V

IN

-------------------

⋅

=

C

F

1

π R

F

F

LC

⋅⋅

-----------------------------

=

C

P

C

F

2

π R

F

C

F

F

ESR

1

–

⋅⋅⋅

----------------------------------------------------------

=

R

S

R

FB

F

SW

2F

⋅

LC

------------------

1

–

---------------------------

=

C

S

1

π R

S

F

SW

⋅⋅

-------------------------------

=