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L6727 数据表(PDF) 21 Page - STMicroelectronics |
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L6727 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 34 page ![]() L6727 Application information Doc ID 12933 Rev 4 21/34 10.2 Output capacitors Output capacitors choice depends on the application constraints in point of output voltage ripple and output voltage deviation during a load transient. During steady-state conditions, the output voltage ripple is influenced by ESR and capacitance of the output capacitors as follows: Where ΔI L is the inductor current ripple. These contribution are not in phase, so total ripple will be lower than the sum of their moduli. Even ESL and board parasitic inductance can contribute significantly to output ripple. During a load variation, the output capacitors supply to the load the additional current or absorb the current in excess delivered by the inductor until converter reaction is completed. In fact, even if the controller react immediately to the load transient saturating the duty cycle to 80 % or 0 %, the current slew rate is limited by the inductance. At first approximation, output voltage drop, based on ESR and capacitor charge/discharge and considering an ideal load-step, can be estimated as follows: Where ΔV L is the voltage applied to the inductor during the transient ( for the load appliance or VOUT for the load removal). MLCC capacitors typically have low ESR to minimize the ripple but also have low capacitance that do not minimize the capacitive voltage deviation during load transient. On the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive voltage deviation during load transient, but also higher ESR value resulting in higher ripple voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in dynamic conditions. 10.3 Input capacitors The input capacitor bank is designed mainly to stand input rms current, which depends on output current (IOUT) and duty-cycle (D) for the regulation as follows: The equation reaches its maximum value, IOUT/2, when D = 0.5. Losses depend on input capacitor ESR: ΔV OUT_ESR ΔI L ESR ⋅ = ΔV OUT_C ΔI L 1 8C OUT F SW ⋅⋅ --------------------------------------- ⋅ = ΔV OUT_ESR ΔI OUT ESR ⋅ = ΔV OUT_C L ΔI OUT 2 ⋅ 2C OUT ΔV L ⋅⋅ -------------------------------------- = D MAX V IN V OUT – ⋅ I rms I OUT D1 D – () ⋅ ⋅ = PESR I rms 2 ⋅ = |
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