SC1155

PROGRAMMABLE SYNCHRONOUS

DC/DC HYSTERETIC CONTROLLER

WITH VRM 9.0 VID RANGE

© 2000 SEMTECH CORP.

PRELIMINARY - August 7, 2000

13

Reference/Voltage Identification

The reference/voltage identification (VID) section con-

sists of a temperature compensated bandgap refer-

ence and a 5-bit voltage selection network. The 5 VID

pins are TTL compatable inputs to the VID selection

network. They are internally pulled up to +5V gener-

ated from the +12V supply by a resistor divider, and

provide programmability of output voltage from 1.1V to

1.85V in 25mV increments.

Refer to the Output Voltage Table for the VID code

settings. The output voltage of the VID network, VREF

is within 1% of the nominal setting over the full input

and output voltage range and junction temperature

range.

The output of the reference/VID network is

indirectly brought out through a buffer to the REFB pin.

The voltage on this pin will be within 3mV of VREF. It is

not recommended to drive loads with REFB other than

setting the hysteresis of the hysteretic comparator,

because the current drawn from REFB sets the charg-

ing current for the soft start capacitor. Refer to the soft

start section for additional information.

Hysteretic Comparator

The hysteretic comparator regulates the output voltage

of the synchronous-buck converter. The hysteresis is

set by connecting the center point of a resistor divider

from REFB to AGND to the HYST pin. The hysteresis

of the comparator will be equal to twice the voltage

difference between REFB and HYST, and has a maxi-

mum value of 60mV. The maximum propagation delay

from the comparator inputs to the driver outputs is

250ns.

Low Side Driver

The low side driver is designed to drive a low R

DS(ON)

N-channel MOSFET, and is rated for 2 amps source

and sink current. The bias for the low side driver is

provided internally from VDRV.

High Side Driver

The high side driver is designed to drive a low R

DS(ON)

N-channel MOSFET, and is rated for 2 amps source

and sink current.

It can be configured either as a

ground referenced driver or as a floating bootstrap

driver. When configured as a floating driver, the bias

voltage to the driver is developed from the DRV regula-

tor. The internal bootstrap diode, connected between

the DRV and BOOT pins, is a Schottky for improved

drive efficiency.

The maximum voltage that can be

applied between the BOOT pin and ground is 25V. The

driver can be referenced to ground by connecting

BOOTLO to PGND, and connecting +12V to the BOOT

pin.

Deadtime Control

Deadtime control prevents shoot-through current from

flowing through the main power FETs during switching

transitions by actively controlling the turn-on times of

the FET drivers. The high side driver is not allowed to

turn on until the gate drive voltage to the low-side FET

is below 2 volts. The low side driver is not allowed to

turn on until the voltage at the junction of the 2 FETs

(VPHASE) is below 2 volts. An internal low-pass filter

with an 11MHz pole is located between the output of

the low-side driver (DL) and the input of the deadtime

circuit. This controls the high-side driver by filtering out

the noise that could appear on DL when the high-side

driver turns on.

Current Sensing

Current sensing is achieved by sampling and holding

the voltage across the high side FET while it is turned

on. The sampling network consists of an internal 50

Ω

switch and an external 0.1µF hold capacitor. Internal

logic controls the turn-on and turn-off of the sample/

hold switch such that the switch does not turn on until

VPHASE transitions high and turns off when the input

to the high side driver goes low. Thus sampling will

occur only when the high side FET is conducting cur-

rent.

The voltage at the IO pin equals 2 times the

sensed voltage. In applications where a higher accu-

racy in current sensing is required, a sense resistor can

be placed in series with the high side FET and the

voltage across the sense resistor can be sampled by

the current sensing circuit.

Droop Compensation

The droop compensation network reduces the load

transient overshoot/undershoot at VOUT, relative to

VREF. VOUT is programmed to a voltage greater than

VREF (equal to VREF x (1+R5/R6)) by an external

resistor divider from VOUT to the VSENSE pin to

reduce the undershoot on VOUT during a low to high

load current transient. The overshoot during a high to

low load current transient is reduced by subtracting the

voltage that is on the DROOP pin from VREF. The

voltage on the IO pin is divided down with an external

FUNCTIONAL DESCRIPTION