SC1155

PROGRAMMABLE SYNCHRONOUS

DC/DC HYSTERETIC CONTROLLER

WITH VRM 9.0 VID RANGE

© 2000 SEMTECH CORP.

PRELIMINARY - August 7, 2000

14

FUNCTIONAL DESCRIPTION (cont.)

resistor divider, and connected to the DROOP pin.

Thus, under loaded conditions, VOUT is regulated to

Vout = Vref • (1+R7/R8) - IOUT • R2/(R1+R2).

Inhibit

The inhibit pin is a TTL compatible digital pin that is

used to enable the controller. When INH is low, the

output drivers are low, the soft start capacitor is dis-

charged, the soft start current source is disabled, and

the controller is in a low I

When INH goes high,

the short across the soft start capacitor is removed, the

soft start current source is enabled, and normal con-

verter operation begins. When the system logic supply

is connected to INH, it controls power sequencing by

locking out controller operation until the system logic

supply exceeds the input threshold voltage of the INH

circuit; thus the +12V supply and the system logic

supply (either +5V or 3.3V) must be above UVLO

thresholds before the controller is allowed to start up.

VIN

The VIN undervoltage lockout circuit disables the con-

troller while the +12V supply is below the 10V start

threshold during power-up.

While the controller is

disabled, the output drivers will be low, the soft start

capacitor will be shorted and the soft start current is

disabled and the controller will be in a low I

When VIN exceeds the start threshold, the short across

the soft start capacitor is removed, the soft start current

source is enabled and normal converter operation be-

gins.

There is a 2V hysteresis in the undervoltage

lockout circuit for noise immunity.

Soft Start

The soft start circuit controls the rate at which VOUT

powers up. A capacitor is connected between SS and

AGND and is charged by an internal current source.

The value of the current source is proportional to the

reference voltage so the charging rate of C

proportional to the reference voltage. By making the

charging current proportional to VREF, the power-up

time for VOUT will be independent of VREF. Thus, C

SS

can remain the same value for all VID settings. The

soft start charging current is determined by the follow-

ing equation: I

Where I

flowing out of the REFB pin. It is recommended that no

additional loads be connected to REFB, other than the

resistor divider for setting the hysteresis voltage. Thus

these resistor values will determine the soft start charg-

ing current. The maximum current that can be sourced

by REFB is 500µA.

Power Good

The power good circuit monitors for an undervoltage

condition on VOUT. If VSENSE is 7% (nominal) below

VREF, then the power good pin is pulled low.

The

PWRGD pin is an open drain output.

Overvoltage Protection

The overvoltage protection circuit monitors VOUT for

an overvoltage condition.

If VSENSE is 15% above

VREF, than a fault latch is set and both output drivers

are turned off. The latch will remain set until VIN goes

below the undervoltage lockout value. A 1ms deglitch

timer is included for noise immunity.

Overcurrent Protection

The overcurrent protection circuit monitors the current

through the high side FET. The overcurrent threshold

is adjustable with an external resistor divider between

IO and AGND, with the divider voltage connected to the

OCP pin.

If the voltage on the OCP pin exceeds

100mV, then a fault latch is set and the output drivers

are turned off. The latch will remain set until VIN goes

below the undervoltage lockout value. A 1ms deglitch

timer is included for noise immunity. The OCP circuit is

also designed to protect the high side FET against a

short-to-ground fault on the terminal common to both

power FETs (VPHASE).

Drive Regulator

The drive regulator provides drive voltage to the low

side driver, and to the high side driver when the high

side driver is configured as a floating driver.

The

minimum drive voltage is 7V.

The minimum short

circuit current is 100mA.