SC1155

PROGRAMMABLE SYNCHRONOUS

DC/DC HYSTERETIC CONTROLLER

WITH VRM 9.0 VID RANGE

© 2000 SEMTECH CORP.

PRELIMINARY - August 7, 2000

16

MATERIALS LIST

Quantity

Reference

Part/Description

Vendor

Notes

1

C5

0.001µF

6

C1-C4, C8, C11

0.01µF

3

C17-C19

150µF, 16V (TPS)

AVX

7

C6,C7,C9,C12,C16,C20, C27

0.1µF

2

C13,C14

0.33µF

6

C21-C26

150µF, 4V, (PosCap)

Sanyo

2

C10,C15

2.2µF, 16V

1

D1

MBRD1035

MOT

1

L1

1µH, DO5022P-102

Coilcraft

1

L2

1.5µH, DO5022P-152HC

Coilcraft

1

Q1

IRL3103NS, D2PAK

Int. Rect.

1

Q2

IRL2203NS, D2PAK

Int. Rect.

2RA,RB

0

Ω

1R1

2K

2

R2,R4

1K

1R3

2.7K

1

R5

100

1

R6

20K

1

R7

150

3

R8,R9,R10

10K

1

R11

2.2

1

R12

3.9

1

U1

SC1155, SO-28

SEMTECH

Layout guidelines

1. Locate R8 and C5 close to pins 6 and 7.

2. Locate C6 close to pins 5 and 7.

3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be refer-

enced to AGND.

4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND.

5. Locate bootstrap capacitor C13 close to the IC.

6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective.

7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise.

8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin.

9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple cur-

rent flow in this pass.

10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower

Vout settings, it needs to be placed next to the aforementioned FET in very close proximity.

11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be

achieved by connecting the AGND to the ground side of the bulk output capacitors.

12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple

vias.

13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the

chip with the cathode connected to BOOTLO and anode connected to DRVGND.