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TMS570LS3137 数据表(PDF) 80 Page - Texas Instruments |
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TMS570LS3137 数据表(HTML) 80 Page - Texas Instruments |
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80 / 159 page  EVEN Address TCMBUS ODD Address TCMBUS 64Bitdatabus 64Bitdatabus Upper32bits data& 4ECCbits Lower 32bits data& 4ECCbits 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM Upper32bits data& 4ECCbits Lower 32bits data& 4ECCbits 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM 36Bit wide RAM TCRAM Interface1 PMT I/F VBUSP I/F CortexR4F™ B0 TCM B1 TCM A TCM TCRAM Interface2 PMT I/F VBUSP I/F TMS570LS3137 SPNS162. – SEPTEMBER 2011 www.ti.com 4.11 Tightly-Coupled RAM Interface Module Figure 4-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F ™ CPU. Figure 4-10. TCRAM Block Diagram 4.11.1 Features The features of the Tightly Coupled RAM (TCRAM) Module are: • Acts as slave to the Cortex-R4F CPU's BTCM interface • Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code • Monitors CPU Event Bus and generates single or multi-bit error interrupts • Stores addresses for single and multi-bit errors • Supports RAM trace module • Provides CPU address bus integrity checking by supporting parity checking on the address bus • Performs redundant address decoding for the RAM bank chip select and ECC select generation logic • Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks • Supports auto-initialization of the RAM banks along with the ECC bits • No support for bit-wise RAM accesses 4.11.2 TCRAMW ECC Support The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The TCRAMW monitors the CPU's event bus and provides registers for indicating single/multi-bit errors and also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU. For more information see the TMS570LS31X/21X Technical Reference Manual (SPNU499). 4.12 Parity Protection for Accesses to peripheral RAMs Accesses to all peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error. 80 System Information and Electrical Specifications Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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