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TMS570LS3137 数据表(PDF) 93 Page - Texas Instruments |
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TMS570LS3137 数据表(HTML) 93 Page - Texas Instruments |
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93 / 159 page  TMS570LS3137 www.ti.com SPNS162. – SEPTEMBER 2011 Table 4-31. Interrupt Request Assignments (continued) Modules Interrupt Sources Default VIM Interrupt Channel Ethernet C0_RX_PULSE 79 HWAG1 HWA_INT_REQ_H 80 HWAG2 HWA_INT_REQ_H 81 DCC1 DCC done interrupt 82 DCC2 DCC2 done interrupt 83 Reserved Reserved 84-87 HWAG1 HWA_INT_REQ_L 88 HWAG2 HWA_INT_REQ_L 89 Reserved Reserved 90-95 NOTE Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..94 can be used and are offset by 1 address in the VIM RAM. NOTE The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise" interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt condition is indicated as soon as the device is powered up. This can be ignored if the EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used in the application, then the external slave memory must always drive the EMIF_nWAIT signal such that an interrupt is not caused due to the default pull-up on this signal. NOTE The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels. NOTE The application can change the mapping of interrupt sources to the interrupt channels via the interrupt channel control registers (CHANCTRLx) inside the VIM module. Copyright © 2011, Texas Instruments Incorporated System Information and Electrical Specifications 93 Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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