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TMS570LS3137 数据表(PDF) 133 Page - Texas Instruments |
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TMS570LS3137 数据表(HTML) 133 Page - Texas Instruments |
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133 / 159 page ![]() TMS570LS3137 www.ti.com SPNS162. – SEPTEMBER 2011 Table 5-16. FlexRay Jitter Timing(1) Parameter MIN MAX Unit tTx1bit Clock jitter and signal symmetry 98 102 ns tTx10bit FlexRay BSS (byte start sequence) to BSS 999 1001 ns tTx10bitAvg Average over 10000 samples 999.5 1000.5 ns tRxAsymDelay (2) Delay difference between rise and fall from Rx pin to sample – 2.5 ns point in FlexRay core tjit(SCLK) Jitter for the 80MHz Sample Clock generated by the PLL – 0.5 ns (1) This parameter will be characterized, but not production-tested. (2) This value is based on design simulation. 5.5.3 FlexRay Transfer Unit The FlexRay Transfer Unit is able to transfer data between the input buffer (IBF) and output buffer (OBF) of the communication controller and the system memory without CPU interaction. Because the FlexRay module is accessed through the FTU, the FTU must be powered up by the setting bit 23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay module register. For more information on the FTU see the TMS570LS31X/TMS570LS21X Technical Reference Manual (SPNU499). Copyright © 2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 133 Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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