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DS80C310 数据表(PDF) 15 Page - Dallas Semiconductor |
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DS80C310 数据表(HTML) 15 Page - Dallas Semiconductor |
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15 / 22 page ![]() DS80C310 15 of 22 Note 2: Address is held in a weak latch until overdriven by external memory. EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS Clock High Time tCHCX 10 ns Clock Low Time tCLCX 10 ns Clock Rise Time tCLCL 5 ns Clock Fall Time tCHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SM2 = 0, 12 clocks per cycle 12tCLCL Serial Port Clock Cycle Time tXLXL SM2 = 1, 4 clocks per cycle 4tCLCL ns SM2 = 0, 12 clocks per cycle 10tCLCL Output Data Setup to Clock Rising tQVXH SM2 = 1, 4 clocks per cycle 3tCLCL ns SM2 = 0, 12 clocks per cycle 2tCLCL Output Data Hold from Clock Rising tXHQX SM2 = 1, 4 clocks per cycle tCLCL ns SM2 = 0, 12 clocks per cycle tCLCL Input Data Hold after Clock Rising tXHDX SM2 = 1, 4 clocks per cycle tCLCL ns SM2 = 0, 12 clocks per cycle 11tCLCL Clock Rising Edge to Input Data Valid tXHDV SM2 = 1, 4 clocks per cycle 3tCLCL ns DEFINITION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following are description of the symbols. t Time A Address C Clock D Input Data H Logic Level High L Logic Level Low I Instruction P PSEN Q Output Data R RD Signal V Valid W WR Signal X No longer a valid logic level Z Tri-State |
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