ICS951702 datasheet(5/12 Pages) IDT | PIII??System Clock Chip for DDR SDRAM

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ICS951702 数据表(PDF) 5 Page - Integrated Device Technology

部件名	ICS951702

功能描述	PIII??System Clock Chip for DDR SDRAM

PDF	12 Pages

Scroll/Zoom	100%

制造商	IDT [Integrated Device Technology]

网页	http://www.idt.com

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ICS951702 数据表(HTML) 5 Page - Integrated Device Technology

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5

ICS951702

Advance Information

0664—07/29/02

Byte 1: Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

#

3

S

F

6

t

i

B0

11

1

P

G

A

5

t

i

B9

1

0

P

G

A

4

t

i

B8

21

z

H

M

8

4

3

t

i

B2

1

C

I

P

A

O

I

2

t

i

B5

51

F

_

K

L

C

U

P

C

1

t

i

B4

51

0

K

L

C

U

P

C

0

t

i

B3

51

1

K

L

C

U

P

C

Byte 2: Active/Inactive Register

(1= enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

Byte 4: Active/Inactive Register

(1= enable, 0 = disable)

Byte 5: Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: Active/Inactive Register

(1= enable, 0 = disable)

Byte 6: Active/Inactive Register

(1= enable, 0 = disable)

Note: Don’t write into this register, writing into this

register can cause malfunction

T

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B#

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1

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2

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2

=

0

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1

;

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