Integrated

Circuit

Systems, Inc.

ICS951702

Advance Information

0664—07/29/02

Block Diagram

Functionality

Pin Configuration

56-Pin 240 mil TSSOP

Recommended Application:

1644 and 1644T applications using DDR

Output Features:

•

7 - Differential pairs DDR SDRAM clocks

•

3 - CPU @ 2.5V (1 - Free running)

•

8 - PCI @ 3.3V (1 - Free running and 1 - 2 X optional)

•

2 - AGP @ 3.3V

•

1 - IOAPIC @ 2.5V

•

1 - 48MHz, @3.3V

•

1 - REF @ 3.3V

Features:

•

Up to 147MHz frequency support

•

Power management through PD#

•

Spread spectrum for EMI control (0 to -0.5% down

spread, ± 0.25% center spread).

•

Uses external 14.318MHz crystal

Skew Specifications:

•

CPU - CPU: <250ps

•

PCI - PCI: <500ps

•

SDRAM - SDRAM: <250ps

•

AGP - AGP: <250ps

•

PCI - AGP: <750ps

•

CPU - SDRAM: <750ps

•

CPU - PCI: <3ns

PIII™ System Clock Chip for DDR SDRAM

Notes:

* Internal Pull-up Resistor of 120K to VDD

** Internal Pull-down of 120K to GND

1. PCICLK6 is selectable 2X via I

Note:

PCICLK = 33.33MHz

AGP = 66.66MHz

FS3

FS2

FS1

FS0

CPU

SDRAM

0

0

0

0

66.66

66.66

0

0

0

1

66.66

100.00

0

0

1

0

100.00

66.66

0

0

1

1

100.00

100.00

0

1

0

0

100.00

133.33

0

1

0

1

133.33

66.66

0

1

1

0

133.33

100.00

0

1

1

1

133.33

133.33

1

0

0

0

66.66

66.66

1

0

0

1

66.66

100.00

1

0

1

0

100.00

66.66

1

0

1

1

100.00

100.00

1

1

0

0

100.00

133.33

1

1

0

1

133.33

66.66

1

1

1

0

133.33

100.00

1

1

1

1

133.33

133.33

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

VDDL

IOAPIC

GND

X1

X2

AVDD

FS0/REF

VDD

PCICLK0

PCICLK1

PCICLK2

GND

VDD

**

**FS1/AGP0

AGP1

GND

**FS2/PCI_F

PCICLK3

PCICLK4

PCICLK5

GND

VDD

PCICLK6

*PCI_STOP#

*CPU_STOP#

*Vtt_PWRGD/PD#

VDD

**FS3/48MHz

1

VDDL

CPUCLK_F

CPUCLK0

CPUCLK1

GND

DDRT0

DDRC0

GND

VDDL

SCLK

SDATA

GND

DDRT1

DDRC1

DDRT2

DDRC2

VDDL

GND

DDRT3

DDRC3

DDRT4

DDRC4

GND

VDDL

DDRT5

DDRC5

DDRT6

DDRC6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Vtt_PWRGD/PD#

MODE

SDATA

SCLK

FS (3:0)

PLL2

PLL1

Spread

Spectrum

48MHz

CPUCLK (1:0)

IOAPIC

AGP (1:0)

2

2

X1

X2

XTAL

OSC

CPU

DIVDER

AGP

DIVDER

REF0

Control

Logic

Config.

Reg.

SDRAM

DIVDER

DDRC (6:0)

DDRT (6:0)

7

7

PCICLK (6:0)

5

PCICLK_F

PCI

DIVDER

Stop

Stop

CPUCLK_F