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ICS951702 数据表(PDF) 10 Page - Integrated Device Technology |
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ICS951702 数据表(HTML) 10 Page - Integrated Device Technology |
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10 / 12 page ![]() 10 ICS951702 Advance Information 0664—07/29/02 1. The ICS clock generator is a slave/receiver, I 2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Controlle r (Host) ICS (Sla ve /Re ce ive r) Start Bit Address D2(H) ACK Dumm y Comm and Code ACK Dumm y Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 ACK Stop Bit How to Write: Controlle r (Host) ICS (Sla ve /Re ce ive r) Start Bit Address D3(H) ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit How to Read: General I 2C serial interface information The information in this section assumes familiarity with I 2C programming. For more information, contact ICS for an I 2C programming application note. How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends a dummy command code • ICS clock will acknowledge • Controller (host) sends a dummy byte count • ICS clock will acknowledge • Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the byte count • Controller (host) acknowledges • ICS clock sends first byte (Byte 0) through byte 7 • Controller (host) will need to acknowledge each byte • Controller (host) will send a stop bit Notes: |
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