L3GD20 datasheet(34/44 Pages) STMICROELECTRONICS

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L3GD20

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Doc ID 022116 Rev 1

7.5

CTRL_REG4 (23h)

7.6

CTRL_REG5 (24h)

Table 28.

CTRL_REG4 register

BDU

BLE

FS1

FS0

0(1)

This value must not be changed.

0(1)

SIM

Table 29.

CTRL_REG4 description

BDU

Block data update. Default value: 0

(0: continuos update; 1: output registers not updated until MSb and LSb read-

ing)

BLE

Big/little endian data selection. Default value 0.

(0: Data LSb @ lower address; 1: Data MSb @ lower address)

FS1-FS0

Full scale selection. Default value: 00

(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)

SIM

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 30.

CTRL_REG5 register

BOOT

FIFO_EN

HPen

INT1_Sel1

INT1_Sel0

Out_Sel1

Out_Sel0

Table 31.

CTRL_REG5 description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

HPen

High-pass filter enable. Default value: 0

(0: HPF disabled; 1: HPF enabled See Figure 20)

INT1_Sel1-

INT1_Sel0

INT1 selection configuration. Default value: 0

(See

Figure 20)

Out_Sel1-

Out_Sel1

Out selection configuration. Default value: 0

(See

Figure 20)

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