L3GD20 datasheet(40/44 Pages) STMICROELECTRONICS

40 / 44 page

L3GD20

40/44

Doc ID 022116 Rev 1

7.21

INT1_THS_ZH (36h)

7.22

INT1_THS_ZL (37h)

7.23

INT1_DURATION (38h)

The D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration

steps and maximum values depend on the ODR chosen.

The WAIT bit has the following definitions:

Wait = ‘0’: the interrupt falls immediately if the signal crosses the selected threshold

Wait = ‘1’: if the signal crosses the selected threshold, the interrupt falls only after the

duration has counted the number of samples at the selected data rate, written into the

duration counter register.

Table 55.

INT1_THS_ZH register

THSZ14

THSZ13

THSZ12

THSZ11

THSZ10

THSZ9

THSZ8

Table 56.

INT1_THS_ZH description

THSZ14 - THSZ9

Interrupt threshold. Default value: 0000 0000

Table 57.

INT1_THS_ZL register

THSZ7

THSZ6

THSZ5

THSZ4

THSZ3

THSZ2

THSZ1

THSZ0

Table 58.

INT1_THS_ZL description

THSZ7 - THSZ0

Interrupt threshold. Default value: 0000 0000

Table 59.

INT1_DURATION register

WAIT

Table 60.

INT1_DURATION description

WAIT

WAIT enable. Default value: 0 (0: disable; 1: enable)

D6 - D0

Duration value. Default value: 000 0000

L3GD20 数据表(PDF) 40 Page - STMicroelectronics

L3GD20 数据表(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载