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ISL97649AIRZ 数据表(PDF) 7 Page - Intersil Corporation

部件名 ISL97649AIRZ
功能描述  TFT-LCD Supply DCP VCOM Amplifier Gate Pulse Modulator RESET
PDF  20 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

ISL97649AIRZ 数据表(HTML) 7 Page - Intersil Corporation

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ISL97649A
7
FN7928.0
December 5, 2011
ISC
Output Short Circuit Current
Pull-up
150
225
mA
Pull-down
150
200
mA
SR
Slew Rate
25
V/µs
BW
Gain Bandwidth
-3dB gain point
20
MHz
DIGITAL CONTROLLED POTENTIOMETER
SETVR
(Note 12)
SET Voltage Resolution
8Bits
SETDNL
(Note 8, 9,
14)
SET Differential Nonlinearity
TA = +25°C
±1
LSB
SETZSE
(Note 10, 14)
SET Zero-Scale Error
TA = +25°C
±2
LSB
SETFSE
(Note 11,14)
SET Full-Scale Error
TA = +25°C
±8
LSB
IRSET
RSET Current
100
µA
AVDD to SET AVDD to SET Voltage Attenuation
1:20
V/V
FAULT DETECTION THRESHOLD
VUVLO
Undervoltage Lock out Threshold
PVIN rising
2.25
2.33
2.41
V
PVIN falling
2.125
2.20
2.27
V
OVPAVDD
(Note 13)
Boost Overvoltage Protection Off
Threshold to Shutdown IC
15.0
15.5
16.0
V
TOFF
Thermal Shut-Down all Channels
Temperature rising
153
°C
POWER SEQUENCE TIMING
tssVLOGIC
VLOGIC Soft-start Time
0.45
ms
Iss
Boost Soft-start Current
3
5.5
8
µA
Electrical Specifications VIN = ENABLE = 3.3V, AVDD =8V, VLDO = 2.5V, VON =24V, VOFF = - 6V. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6) UNITS
Serial Interface Specifications For SCL and SDA Unless Otherwise Noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
(Note 7)
MAX
(Note 14)
UNITS
fSCL
(Note 6)
SCL Frequency
400
kHz
tiN
(Note 6)
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VIN, until
SDA exits the 30% to 70% of VIN window
480
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VIN during
the following START condition
480
ns
tLOW
Clock LOW Time
Measured at the 30% of VIN crossing
480
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VIN crossing
400
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
crossing 70% of VIN
480
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VIN to
SCL falling edge crossing 70% of VIN
400
ns



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