ISL97649A

13

FN7928.0

December 5, 2011

Gate Pulse Modulator Circuit

The gate pulse modulator circuit functions as a three way

multiplexer, switching VGHM between ground, GPM_LO and VGH.

Voltage selection is provided by digital inputs VDPM (enable) and

VFLK (control). High to low delay and slew control is provided by

external components on pins CE and RE, respectively.

When VDPM is LOW, the block is disabled and VGHM is

grounded. When the input voltage exceeds UVLO threshold,

VDPM starts to drive an external capacitor. Once VDPM exceeds

1.215V, the GPM circuit is enabled, and the output VGHM is

determined by VFLK, RESET signal and VGH voltage. If RESET

signal is high and VFLK is high, VGHM is pulled to VGH. When

VFLK goes low, there is a delay controlled by capacitor CE,

following which, VGHM is driven to GPM_LO, with a slew rate

controlled by resistor RE. Note that GPM_LO is used only as a

reference voltage for an amplifier, and thus does not have to

source or sink a significant DC current.

Low to high transition is determined primarily by the switch

resistance and the external capacitive load. High to low transition

is more complex. Take the case where the block is already

enabled (VDPM is H). When VFLK is H, if CE is not externally

pulled above threshold voltage 1, pin CE is pulled low. On the

falling edge of VFLK, a current is passed into pin CE to charge the

external capacitor up to threshold voltage 2, providing a delay

which is adjustable by varying the capacitor on CE. Once this

threshold is reached, the output starts to be pulled down from

VGH to GPM_LO. The maximum slew current is equal to 500/(RE

load capacitance applied to VGHM. The slew rate reduces as

VGHM approaches GPM_LO.

If CE is always pulled up to a voltage above threshold 1, zero

delay mode is selected; thus, there will be no delay from FLK

falling to the point where VGHM starts to fall. Slew down currents

will be identical to the previous case.

At power-down, when VIN falls to UVLO, VGHM will be tied to VGH

until the VGH voltage falls to 3V. Once the VGH voltage falls below

3V, VGHM will not be actively driven until VIN is driven. Figure 14

VCOM Amplifier

The VCOM amplifier is designed to control the voltage on the back

plane of an LCD display. This plane is capacitively coupled to the

pixel drive voltage, which alternately cycles positive and negative at

the line rate for the display. Thus, the amplifier must be capable of

sourcing and sinking pulses of current, which can occasionally be

quite large (in the range of 100mA for typical applications).

The ISL97649A VCOM amplifier's output current is limited to

225mA typical. This limit level, which is roughly the same for

sourcing and sinking, is included to maintain reliable operation

of the part. It does not necessarily prevent a large temperature

rise if the current is maintained. (In this case, the whole chip may

be shut down by the thermal trip to protect functionality.) If the

display occasionally demands current pulses higher than this

limit, the reservoir capacitor will provide the excess and the

amplifier will top the reservoir capacitor back up once the pulse

has stopped. This will happen in the µs time scale in practical

systems and for pulses 2 or 3 times the current limit; the VCOM

voltage will have settled again before the next line is processed.

DCP Memory Description

The ISL97649A contains one non-volatile byte known as the

operations with Address 00h. The IVR contains the value that is

loaded into the Volatile Wiper Register (WR) at power-up.

The volatile WR and the non-volatile IVR of a DCP are accessed

with the same address.

The Access Control Register (ACR) determines which word at

address 00h is accessed (IVR or WR). The volatile ACR must be

set as follows:

When the ACR is all zeroes, which is the default at power-up:

• A read operation to address 0 outputs the value of the

non-volatile IVR.

VGH_M is forced to

VGH when RESET

goes to low AND

VGH>3V

Power on delay time

is controlled by

Slope is controlled

by RE

Delay time is controlled

by CE

FIGURE 14. GATE PULSE MODULATOR TIMING DIAGRAM

VIN

UVLO

0

VGH

RESET

VDPM

VFLK

VGHM

THRESHOLD

VGH

GPM_LO

POWER-ON DELAY TIME

SLOPE IS

CONTROLLED BY RE

DELAY TIME IS

CONTROLLED BY CE

VGHM IS FORCED

TO VGH WHEN VIN

1.215V

FALLS TO UVLO AND

VGH>3V