ISL97649A

14

FN7928.0

December 5, 2011

• A write operation to address 0 writes the identical values to the

WR and IVR of the DCP.

• When the ACR is 80h:

- A read operation to address 0 outputs the value of the

volatile WR.

- A write operation to address 0 only writes to the

volatile WR.

It is not possible to write to an IVR without writing the same value

to its WR.

00h and 80h are the only values that should be written to

address 2. All other values are reserved and must not be written

to address 2.

The ISL97649A supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data on to the bus as

a transmitter and the receiving device as the receiver. The device

controlling the transfer is a master and the device being

controlled is the slave. The master always initiates data transfers

and provides the clock for both transmit and receive operations.

Therefore, the DCP of the ISL97649A operates as a slave device

in all applications. The fall and rise time of SDA and SCL signal

bus is also specified in Table 8.

the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (see Figure 15). On

power-up of the ISL97649A, the SDA pin is in the input mode.

which is a HIGH to LOW transition of SDA while SCL is HIGH. The

DCP continuously monitors the SDA and SCL lines for the START

condition and does not respond to any command until this

condition is met (see Figure 15). A START condition is ignored

during the power-up sequence and during internal non-volatile

write cycles.

is a LOW to HIGH transition of SDA while SCL is high (see

Figure 15). A STOP condition at the end of a read operation, or at

the end of a write operation to volatile bytes only places the

device in its standby mode. A STOP condition during a write

operation to a non-volatile write byte, initiates an internal

non-volatile write cycle. The device enters its standby state when

the internal non-volatile write cycle is completed.

An ACK (Acknowledge) is a software convention used to indicate a

successful data transfer. The transmitting device, either master or

slave, releases the SDA bus after transmitting eight bits. During the

ninth clock cycle, the receiver pulls the SDA line LOW to

acknowledge the reception of the eight bits of data (see Figure 16).

The ISL97649A DCP responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and once

again after successful receipt of an Address Byte. The ISL97649A

also respond with an ACK after receiving a Data Byte of a write

operation. The master must respond with an ACK after receiving

a Data Byte of a read operation.

A valid Identification Byte contains 0101000 as the seven MSBs.

The LSB is in the Read/Write bit. Its value is "1" for a Read

operation, and "0" for a Write operation (see Table 7).

Write Operation

A write operation requires a START condition, followed by a valid

Identification Byte, a valid Address Byte, a Data Byte, and a STOP

condition (see Figure 17). After each of the three bytes, the

ISL97649A responds with an ACK. At this time, if the Data Byte is

to be written only to volatile registers, the device enters its

standby state. If the Data Byte is to be written also to non-volatile

memory, the ISL97649A begins its internal write cycle to

non-volatile memory. During the internal non-volatile write cycle,

the device ignores transitions at the SDA and SCL pins and the

SDA output is at high impedance state. When the internal

non-volatile write cycle is completed, the ISL97649A enters its

standby state. The byte at address 02h determines if the Data

Byte is to be written to volatile and/or non-volatile memory.

Data Protection

A STOP condition also acts as a protection of non-volatile

memory. A valid Identification Byte, Address Byte, and total

number of SCL pulses act as a protection of both volatile and

non-volatile registers. During a Write sequence, the Data Byte is

loaded into an internal shift register as it is received. If the

Address Byte is 0 or 2, the Data Byte is transferred to the Wiper

Register (WR) or to the Access Control Register respectively, at

the falling edge of the SCL pulse that loads the last bit (LSB) of

the Data Byte. If the Address Byte is 0, and the Access Control

Register is all zeros (default), then the STOP condition initiates

the internal write cycle to non-volatile memory.

TABLE 6. MEMORY MAP

ADDRESS

NON-VOLATILE

VOLATILE

2-

ACR

1

Reserved

0IVR

WR

WR: Wiper Register, IVR: Initial value Register.

TABLE 7. IDENTIFICATION BYTE FORMAT

0

1

0

1000

R/W

(MSB)

(LSB)

PARAMETER

MIN

TYP

MAX

UNITS

SDA and SCL Rise Time

1000

ns

SDA and SCL Fall Time

300

ns

400

pF