ICS9DB803DFILFT datasheet(2/21 Pages) IDT

2 / 21 page

IDTTM/ICSTM

Eight Output Differential Buffer for PCIe Gen 2

ICS9DB803DI

REV A

06/18/08

ICS9DB803DI

Eight Output Differential Buffer for PCIe for Gen 2

Pin Configuration

Polarity Inversion Pin List Table

SRC_DIV# 1

48 VDDA

VDD 2

47 GNDA

GND 3

46 IREF

SRC_IN 4

45 LOCK

SRC_IN# 5

44 OE_7

OE_0 6

43 OE_4

OE_3 7

42 DIF_7

DIF_0 8

41 DIF_7#

DIF_0# 9

40 OE_INV

GND 10

39 VDD

VDD 11

38 DIF_6

DIF_1 12

37 DIF_6#

DIF_1# 13

36 OE_6

OE_1 14

35 OE_5

OE_2 15

34 DIF_5

DIF_2 16

33 DIF_5#

DIF_2# 17

32 GND

GND 18

31 VDD

VDD 19

30 DIF_4

DIF_3 20

29 DIF_4#

DIF_3# 21

28 HIGH_BW#

BYPASS#/PLL 22

27 DIF_STOP#

SCLK 23

26 PD#

SDATA 24

25 GND

OE_INV = 0

SRC_DIV# 1

48 VDDA

VDD 2

47 GNDA

GND 3

46 IREF

SRC_IN 4

45 LOCK

SRC_IN# 5

44 OE7#

OE0# 643 OE4#

OE3# 742 DIF_7

DIF_0 8

41 DIF_7#

DIF_0# 9

40 OE_INV

GND 10

39 VDD

VDD 11

38 DIF_6

DIF_1 12

37 DIF_6#

DIF_1# 13

36 OE6#

OE1# 14

35 OE5#

OE2# 15

34 DIF_5

DIF_2 16

33 DIF_5#

DIF_2# 17

32 GND

GND 18

31 VDD

VDD 19

30 DIF_4

DIF_3 20

29 DIF_4#

DIF_3# 21

28 HIGH_BW#

BYPASS#/PLL 22

27 DIF_STOP

SCLK 23

26 PD

SDATA 24

25 GND

OE_INV = 1

6OE_0

OE0#

7OE_3

OE3#

OE_1

OE1#

OE_2

OE2#

PD#

DIF_STOP#

DIF_STOP

OE_5

OE5#

OE_6

OE6#

OE_4

OE4#

OE_7

OE7#

Pins

OE_INV

VDD

GND

SRC_IN/SRC_IN#

6,11,19,

31,39

10,18, 25,32

DIF(7:0)

N/A

IREF

Analog VDD & GND for PLL core

Description

Pin Number

Power Groups

ICS9DB803DFILFT 数据表(PDF) 2 Page - Integrated Device Technology

ICS9DB803DFILFT 数据表(HTML) 2 Page - Integrated Device Technology

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