DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H

12/1/08

ICS9P935

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

7

Recommended Operating Condition (see note 1)

Notes:

1.

Unused inputs must be held high or low to prevent them from floating.

2.

DC input signal voltage specifies the allowable DC execution of differential input.

3.

Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required

for switching, where VT is the true input level and VCP is the complementary input level.

4.

at which the differential signal must be crossing.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.3

2.5

2.7

V

DDRT,DDRC

0.4

V

DDRT,DDRC

2.1

V

DC input signal voltage

(note 2)

-0.3

V

DC - DDRT

0.36

V

AC - DDRT

0.7

V

Output differential cross-

voltage (note 4)

V

Input differential cross-

voltage (note 4)

V

High level output

current

-30

mA

Low level output current

-30

mA

Operating free-air

temperature

085

°C

Differential input signal

voltage (note 3)

Low level input voltage

High level input voltage