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ICS9P935 数据表(PDF) 10 Page - Integrated Device Technology |
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ICS9P935 数据表(HTML) 10 Page - Integrated Device Technology |
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10 / 13 page  IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer ICS9P935 REV H 12/1/08 ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer 10 Table 1: 7-Steps Skew Programming Table 7 Step 11 10 01 00 LSB 11 600 ps 500 ps 400 ps 300 ps 10 N/A N/A N/A 200 ps 01 N/A N/A N/A 100 ps 00 N/A N/A N/A 0.0 ps MSB Table 2: 7-Steps Skew Programming Table 7 Step 11 10 01 00 LSB 11 -600 ps -500 ps -400 ps -300 ps 10 N/A N/A N/A -200 ps 01 N/A N/A N/A -100 ps 00 N/A N/A N/A 0.0 ps MSB I 2C Table: Output Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Freq Detect Low Frequency Detect PLL OFF Control RW OFF ON 1 Bit 6 FB_IN/OUT FB_OUT Control RW Disable Enable 1 Bit 5 DDR_T5/C5 Output Control RW Disable Enable 1 Bit 4 DDR_T4/C4 Output Control RW Disable Enable 1 Bit 3 DDR_T3/C3 Output Control RW Disable Enable 1 Bit 2 DDR_T2/C2 Output Control RW Disable Enable 1 Bit 1 DDR_T1/C1 Output Control RW Disable Enable 1 Bit 0 DDR_T0/C0 Output Control RW Disable Enable 1 I 2C Table: Group Skew Control Register Byte 8 Pin # Name Control Function Type0 1 PWD Bit 7 - DDR Skw3 RW 0 Bit 6 - DDR Skw2 RW 0 Bit 5 - DDR Skw1 RW 0 Bit 4 - DDR Skw0 RW 0 Bit 3 - DDR Skw3 RW 0 Bit 2 - DDR Skw2 RW 0 Bit 1 - DDR Skw1 RW 0 Bit 0 - DDR Skw0 RW 0 I 2C Table: Revision ID and Vendor ID Register Byte 10 Pin # Name Control Function Type0 1 PWD Bit 7 - Revision_ID bit 3 RW - - X Bit 6 - Revision_ID bit 2 RW - - X Bit 5 - Revision_ID bit 1 RW - - X Bit 4 - Revision_ID bit 0 RW - - X Bit 3 - Vendor_ID bit3 RW - - 0 Bit 2 - Vendor_ID bit2 RW -- 0 Bit 1 - Vendor_ID bit1 RW -- 0 Bit 0 - Vendor_ID bit0 RW -- 1 I 2C Table: Byte Count Register Byte 15 Pin # Name Control Function Type 0 1 PWD Bit 7 -BC7 RW 0 Bit 6 -BC6 RW 0 Bit 5 -BC5 RW 0 Bit 4 -BC4 RW 0 Bit 3 -BC3 RW 1 Bit 2 -BC2 RW 1 Bit 1 -BC1 RW 1 Bit 0 -BC0 RW 1 I2C Table: All other I2C Registers are Reserved See Table 2: 7-Step Skew Programming Table CLKIN to DDR Skew Control Byte 6 - - - - Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes - - CLKIN to DDR Skew Control - - Rev ID Vendor ID See Table 1: 7-Step Skew Programming Table |
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