DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H

12/1/08

ICS9P935

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

11

Ordering Information

ICS9P935yFLF-T

α

SEATING

PLANE

SEATING

PLANE

A1

A

A2

e

-C-

- C -

b

.10 (.004) C

.10 (.004) C

c

L

INDEX

AREA

INDEX

AREA

12

1 2

N

D

E1

E

209 mil SSOP

MIN

MAX

MIN

MAX

A

--

2.00

--

.079

A1

0.05

--

.002

--

A2

1.65

1.85

.065

.073

b

0.22

0.38

.009

.015

c

0.09

0.25

.0035

.010

D

E

7.40

8.20

.291

.323

E1

5.00

5.60

.197

.220

e

L

0.55

0.95

.022

.037

N

α

0°

8°

0°

8°

VARIATIONS

MIN

MAX

MIN

MAX

28

9.90

10.50

.390

.413

10-0033

SYMBOL

In Millimeters

In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS

SEE VARIATIONS

0.65 BASIC

0.0256 BASIC

Reference Doc.: JEDEC Publication 95, MO-150

SEE VARIATIONS

SEE VARIATIONS

N

D mm.

D (inch)

Example:

Designation for tape and reel packaging

RoHS Compliant (Optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

ICS XXXX y F LF- T