R5F5630ECDLK datasheet(127/165 Pages) RENESAS

127 / 165 page

R01DS0060EJ0100 Rev.1.00

Page 127 of 168

Sep 13, 2011

RX630 Group

5. Electrical Characteristics

5.4.1

Reset Timing

Note: • Do not allow a reset by the signal on the RES# pin during programming or erasure of the ROM or E2 DataFlash memory or

during blank checking of the E2 DataFlash memory. For details, see section 42.14, Usage Notes, in section 42, ROM (Flash

Memory for Code Storage).

Figure 5.11

Reset Input Timing at Power-On

Figure 5.12

Reset Input Timing

Table 5.11

Reset Timing

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

RES# pulse

width

Power-on

tRESWP

—

Figure 5.11

Deep software standby mode

tRESWD

—

Figure 5.12

Software standby mode, low-speed

operating mode 2

tRESWS

1—

—

Other than above

(except for programming or erasure of the

ROM or E2 data-flash memory or blank

checking of the E2 DataFlash memory)

tRESW

200

—

µs

Wait time after RES# cancellation

tRESWT

—

tcyc

Internal reset time

(independent watchdog timer reset, watchdog timer reset,

software reset)

tRESW2

112

—

120

tcyc

VCC

RES#

tRESWP

Internal reset

tRESWT

RES#

Internal reset

tRESWT

tRESWD, tRESWS, tRESW

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