R5F5630ECDLK datasheet(130/165 Pages) RENESAS

130 / 165 page

R01DS0060EJ0100 Rev.1.00

Page 130 of 168

Sep 13, 2011

RX630 Group

5. Electrical Characteristics

5.4.4

Bus Timing

Table 5.14

Bus Timing

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,

ICLK = 8 to 100 MHz, BCLK = 8 to 50 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF

High drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Typ.

Max.

Unit

Address delay time

tAD

—

Figure 5.17 to

Figure 5.22

Byte control delay time

tBCD

—20

CS# delay time

tCSD

—20

ALE delay time

tALED

—20

RD# delay time

tRSD

—20

Read data setup time

tRDS

—

Read data hold time

tRDH

0—

WR# delay time

tWRD

—20

Write data delay time

tWDD

—20

Write data hold time

tWDH

0—

WAIT# setup time

tWTS

—

Figure 5.23

WAIT# hold time

tWTH

0—

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