Micrel

MICRF219

June 2011

2

M9999-060811

(408) 944-0800

Pin Configuration

1

RO1

GNDRF

ANT

GNDRF

Vdd

SQ

SEL0 7

SHDN

16 RO2

SCLK

RSSI

CAGC

CTH

SEL1

DO

GND

15

14

13

12

11

10

9

2

3

4

5

6

8

MICRF219AYQS

Pin Descript

SOP

n N

ion

16-Pin

Q

Pi

ame

Pin Function

1

RO

ut: Reference resonator input connection to pierce oscillator stage. May also

aximum. Internal

e of 7pF to GND during normal operation.

1

be driven by external reference signal of 200mVp-p to 1.5V p-p amplitude m

capacitanc

Reference Oscillator Inp

2

GNDRF

Negative supply connection associated with ANT RF input.

3

ANT

antenna. Internally AC coupled. It is recommended a matching

on.

network with an inductor-to-RF ground be used to improve ESD protecti

Antenna Input: RF signal input from

4

ND

G

RF

Ground connection for ANT RF input.

5

D

lose to the

V D

Positive supply connection for all chip functions. Bypass with 0.1µF capacitor located as c

VDD pin as possible.

6

SQ

l-up pulls the logic-input HIGH when the device is

vel signal is applied the

enabled. Bit D17 sets whether squelch is enabled or disabled when a logic-le

SQ pin. See Squelch Enable Truth-Table on page

Squelch Control Logic-Level Input. An internal pul

7

E

A typical) when not in

dwidth LSB when serial

ined in SLEEP mode.

S L0

Demodulator Filter Bandwidth Select Logic-Level Input. Internal pull-up (3u

shutdown or SLEEP mode. Used in conjunction with SEL1 to control D3 ban

interface contains default setting. It does not need to be def

8

HD

logic-level HIGH places

in low-power shutdown mode. An internal pull-up pulls the logic input HIGH.

S

N

Shutdown control Logic-Level Input. A logic-level LOW enables the device. A

the device

9

N

G D

Negative supply connection for all chip functions except for RF input.

10

DO

ble.

sed as a CMOS Schmitt input

utdown and sleep modes.

A current limited CMOS output during normal operation this pin is also u

for serial interface data. A 25kΩ pull-down is present when device is in sh

Data Input and Output. Demodulated data output. May be blanked until bit checking test is accepta

11

SEL1

pical) pull-up when not in

shutdown or SLEEP mode. Used in conjunction with SEL0, to control D4 bandwidth MSB, when serial

interface contains default setting. It does not need to be defined in SL

de.

Demodulator Filter Bandwidth Select Logic-Level Input: Internal (3uA ty

EEP mo

12

CTH

Demodulation threshold voltage integration capacitor. Capacitor-to-GND sets the settling time for the

demodulation data slicing level. Values above 1nF are recommended and should be optimized for data

rate and data profile.

13

CAGC

AGC filter capacitor. A capacitor, normally greater than 0.47μF, is connected from this pin-to-GND

14

RSSI

Received signal strength indication (output): Output is from a switched capacitor integrating op amp

with 220Ω typical output impedance.

15

SCLK

Serial interface input clock. CMOS Schmitt input. A 25kΩ pull-down is present when device is in

shutdown mode.

16

RO2

Reference resonator connection. Internal capacitance of 7pF to GND during normal operation.