MICRF219_11 datasheet(4/23 Pages) MICREL

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Micrel

MICRF219

June 2011

M9999-060811

(408) 944-0800

apply for VDD

D = 0V, CAGC = 4.7µF, CTH = 0.1µ

X = 433.92 M

erwise noted. Bold values

C. 1kbps data rate (Manchester encoded), refer

ator frequenc

.52127MHz.

Typ.

Max.

Units

Electrical Characteristics (Continued)

Specifications

= 3.3V, GN

F, fR

Hz un ss oth

= 13

indicate –40

°C – TA – 105°

ence oscill

Parameter

Conditi

Min.

Reference Oscillator Input Range

0.2

1.5

VP-P

Reference Oscillator Sourc

) = 0V

300

µA

V(REFOSC

Current

Demodulator

FREFOSC = 9.81563 MHz

165

CTH Source Impedance

120

kΩ

FREFOSC = 13.52127MH

CTH Leakage Current

TA = 25ºC

T = +105ºC

±2

±800

Demodulator Filter Bandwid

, see application section

9400

Programmable

@ 315MHz

117

Demodulator Filter Bandwi

@ 434MHz

e, see application section

625

13000

dth

Programmabl

Digital / Control Functions

DO Pin Output Current

sink @ 0.2 VDD

260

600

µA

As output source @ 0.8 V

Output Rise And Fall Times

CI = 15pF, pin DO, 10-90%

µsec

Input High Voltage

Pins SCLK, DO (As input), SHDN,SEL0,

SEL1,SQ

0.8VDD

Input Low Voltage

Pins SCLK, DO (As input), SHDN, SEL0,

0.2VDD

SEL1,SQ

Output Voltage High

0.8VDD

Output Voltage Low

0.2VDD

RSSI

−100dBm

0.4

RSSI DC Output Voltage Range

−40dBm

2.0

RSSI Response Slope

−110dBm to -40dBm

mV/dB

RSSI Output Current

400

µA

RSSI Output Impedance

250

Ω

RSSI Response Time

50% data duty cycle, input power to Antenna = -

20dBm

0.3

sec

Notes:

eeding the absolute maximum rating may damage the device.

The device is not guaranteed to function outside of its operating rating.

Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device.

Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is defined

as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded) at a data rate of 1kbps.

When data burst does not contain preamble, duty cycle is defined as total duty cycle, including any “quiet” time between data bursts. When data

bursts contain preamble sufficient to charge the slice level on capacitor CTH, then duty cycle is the effective duty cycle of the burst alone. [For

example, 100msec burst with 50% duty cycle, and 100msec “quiet” time between bursts. If burst includes preamble, duty cycle is

TON/(TON+tOFF)= 50%; without preamble, duty cycle is TON/(TON+ TOFF + TQUIET) = 50msec/(200msec)=25%. TON is the (Average number of

1’s/burst) × bit time, and TOFF = (TBURST – TON.)

Exc

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