Quad IF Receiver

Data Sheet

AD6657A

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2011 Analog Devices, Inc. All rights reserved.

FEATURES

11-bit, 200 MSPS output data rate per channel

Integrated noise shaping requantizer

Performance with NSR enabled

SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS

SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS

SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS

Performance with NSR disabled

SNR: 66.5 dBFS to 70 MHz at 185 MSPS

SFDR: 88 dBc to 70 MHz at 185 MSPS

Low power: 1.2 W at 185 MSPS

1.8 V analog supply operation

1.8 V LVDS (ANSI-644 levels) output

1-to-8 integer clock divider

Internal ADC voltage reference

1.75 V p-p analog input range (programmable to 2.0 V p-p)

Differential analog inputs with 800 MHz bandwidth

95 dB channel isolation/crosstalk

Serial port control

User-configurable built-in self test (BIST) capability

Energy saving power-down modes

APPLICATIONS

Communications

Diversity radio and smart antenna (MIMO) systems

Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA

I/Q demodulation systems

General-purpose software radios

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate

frequency (IF) receiver specifically designed to support multiple

antenna systems in telecommunication applications where high

dynamic range performance, low power, and small size are desired.

The device consists of four high performance ADCs and NSR

digital blocks. Each ADC consists of a multistage, differential

pipelined architecture with integrated output error correction

logic. The ADC features a wide bandwidth switched capacitor

sampling network within the first stage of the differential pipeline.

An integrated voltage reference eases design considerations. A

duty cycle stabilizer (DCS) compensates for variations in the

ADC clock duty cycle, allowing the converters to maintain

excellent performance.

Each ADC output is connected internally to an NSR block. The

integrated NSR circuitry allows for improved SNR performance

in a smaller frequency band within the Nyquist bandwidth. The

device supports two different output modes selectable via the

external MODE pin or the serial port interface (SPI).

With the NSR feature enabled, the outputs of the ADCs are

processed such that the AD6657A supports enhanced SNR per-

formance within a limited portion of the Nyquist bandwidth

while maintaining an 11-bit output resolution. The NSR block

can be programmed to provide a bandwidth of either 22%, 33%,

or 36% of the sample clock. For example, with a sample clock

rate of 185 MSPS, the AD6657A can achieve up to 76.0 dBFS

SNR for a 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS

SNR for a 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS

SNR for a 65 MHz bandwidth in the 36% mode.

(General Description continued on Page 3)

VIN+A

DO±AB

D10±AB

VIN–A

PIPELINE

ADC

NOISE SHAPING

REQUANTIZER

VIN+B

VIN–B

PIPELINE

ADC

VIN+C

VIN–C

PIPELINE

ADC

VIN+D

VIN–D

PIPELINE

ADC

SERIAL PORT

REFERENCE

14

11

NOISE SHAPING

REQUANTIZER

PORT A

AD6657A

PORT B

14

11

NOISE SHAPING

REQUANTIZER

14

11

NOISE SHAPING

REQUANTIZER

CLOCK

DIVIDER

14

11

VCMA

VCMB

VCMC

VCMD

SCLK

SDIO

CSB

CLK+

AVDD

AGND

DRVDD

DRGND

CLK–

DO±CD

DCO±AB

DCO±CD

D10±CD

MODE

SYNC

PDWN