AD6657ABBCZ datasheet(24/36 Pages) AD

24 / 36 page

AD6657A

Data Sheet

Rev. 0 | Page 24 of 36

DIGITAL OUTPUTS

The AD6657A output drivers are configured to interface with

LVDS outputs using a DRVDD supply voltage of 1.8 V. The

output bits are DDR LVDS as shown in Figure 2. Applications

that require the ADC to drive large capacitive loads or large

fanouts may require external buffers or latches.

As described in the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI, the data format can be selected for

offset binary or twos complement when using the SPI control.

TIMING

The AD6657A provides latched data with a latency of

nine clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and minimize the

loads placed on them to reduce transients within the AD6657A

because these transients can degrade converter dynamic per-

formance.

The lowest typical conversion rate of the AD6657A is 40 MSPS.

At clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD6657A provides a data clock output (DCO) signal

intended for capturing the data in an external register. The

output data for Channel A and Channel C is valid when DCO

is high; the output data for Channel B and Channel D is valid

when DCO is low (see Figure 2).

Table 11. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

< −VREF − 0.5 LSB

000 0000 0000

100 0000 0000

VIN+ − VIN−

= −VREF

000 0000 0000

100 0000 0000

VIN+ − VIN−

= 0

100 0000 0000

000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

111 1111 1111

011 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

111 1111 1111

011 1111 1111

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