EVAL-ADE7880EBZ datasheet(47/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 47 of 104

The ADE7880 achieves the integration of the active power signal

in two stages (see Figure 74). The process is identical for both

total and fundamental active powers. The first stage accumulates

the instantaneous phase total or fundamental active power at

1.024MHz, although they are computed by the DSP at 8 kHz

rate. Every time a threshold is reached, a pulse is generated and

the threshold is subtracted from the internal register.

The sign of the energy in this moment is considered the sign

of the active power (see the Sign of Active Power Calculation

section for details). The second stage consists of accumulating

the pulses generated at the first stage into internal 32-bit accu-

mulation registers. The content of these registers is transferred

to watt-hour registers, xWATTHR and xFWATTHR, when

these registers are accessed.

THRESHOLD

1 PULSE = 1LSB OF WATTHR[31:0]

FIRST STAGE OF

ACTIVE POWER

ACCUMULATION

PULSES

GENERATED

AFTER FIRST

STAGE

Figure 75. Active Power Accumulation Inside the DSP

Figure 75 explains this process. The threshold is formed by

concatenating the WTHR 8-bit unsigned register to 27 bits

equal to 0. It is introduced by the user and is common for total

and fundamental active powers on all phases. Its value depends

on how much energy is assigned to one LSB of watt-hour regis-

ters. Supposing a derivative of Wh [10n Wh], n as an integer, is

desired as one LSB of the xWATTHR register, WTHR is

computed using the following equation:

3600

PMAX

WTHR

(26)

where:

PMAX = 27,059,678 = 0x19CE5DE as the instantaneous power

computed when the ADC inputs are at full scale.

fS = 1.024 MHz, the frequency at which every instantaneous

power computed by the DSP at 8 kHz is accumulated.

UFS, IFS are the rms values of phase voltages and currents when

the ADC inputs are at full scale.

WTHR register is an 8-bit unsigned number, so its maximum

value is 28 − 1. Its default value is 0x3. Values lower than 3, that

is 2 or 1 should be avoided and 0 should never be used as the

threshold must be a non-zero value.

This discrete time accumulation or summation is equivalent to

integration in continuous time following the description in

Equation 27.

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

Energy

(27)

where:

n is the discrete time sample number.

T is the sample period.

In the ADE7880, the total phase active powers are accumulated in

the AWATTHR, BWATTHR, and CWATTHR 32-bit signed

registers, and the fundamental phase active powers are

accumulated in AFWATTHR, BFWATTHR, and CFWATTHR

32-bit signed registers. The active energy register content can

roll over to full-scale negative (0x80000000) and continue

increasing in value when the active power is positive. Conversely, if

the active power is negative, the energy register underflows to

full-scale positive (0x7FFFFFFF) and continues decreasing in value.

The ADE7880 provides a status flag to signal when one of the

xWATTHR and xFWATTHR registers is half full. Bit 0 (AEHF)

in the STATUS0 register is set when Bit 30 of one of the

xWATTHR registers changes, signifying one of these registers is

half full. If the active power is positive, the watt-hour register

becomes half full when it increments from 0x3FFF FFFF to 0x4000

0000. If the active power is negative, the watt-hour register

becomes half full when it decrements from 0xC000 0000 to

0xBFFF FFFF. Similarly, Bit 1 (FAEHF) in STATUS0 register, is

set when Bit 30 of one of the xFWATTHR registers changes,

signifying one of these registers is half full.

Setting Bits[1:0] in the MASK0 register enable the FAEHF and

AEHF interrupts, respectively. If enabled, the IRQ0 pin is set

low and the status bit is set to 1 whenever one of the energy

registers, xWATTHR (for the AEHF interrupt) or xFWATTHR

(for the FAEHF interrupt), become half full. The status bit is

cleared and the IRQ0 pin is set to logic high by writing to the

STATUS0 register with the corresponding bit set to 1.

Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a

read-with-reset for all watt-hour accumulation registers, that is,

the registers are reset to 0 after a read operation.

Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation register

is 976.5625 ns (1.024MHz frequency). With full-scale sinusoidal

signals on the analog inputs and the watt gain registers set to

0x00000, the average word value from each LPF2 is PMAX =

27,059,678 = 0x19CE5DE. If the WTHR register threshold is set

at 3, its minimum recommended value, the first stage accumulator

generates a pulse that is added to watt-hour registers every

sec

531

024

PMAX

The maximum value that can be stored in the watt-hour

accumulation register before it overflows is 231 − 1 or

0x7FFFFFFF. The integration time is calculated as

Time = 0x7FFF,FFFF × 14.531 μs = 8 hr 40 min 6 sec

(28)

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